brianu@ada-uts.UUCP (12/30/85)
>Mike Taylor ...!{ihnp4,hplabs,amd,sun}!amdahl!mat writes: >For what it's worth, Fujitsu VPs do I-fetch from cache. Operand fetch >proceeds directly from mainstore via load/store pipe(s). The Cray machines also do instruction fetches out of a cache. Instructions are executed from the "instruction buffers". if the required instruction is in the buffers it is issued from there; otherwise a buffer load is performed on the least recently loaded buffer. Although the buffer is always on a 16 word boundry, the buffer is loaded starting with the required instruction so that execution may continue as soon as possible. The Cray 1S has 4 16-word buffers, the XMP has 4 32-word buffers and the Cray 2 has 8 16-word buffers. Each word is 64-bits and is subdivided into 4 16-bit parcels. An instruction can be either 1 or 2 parcels on either the 1S or XMP, while it can be up to 5 parcels on the Cray 2. Unforunately, since the buffer are reloaded in round-robin fashion, it is not possible to maintain a small kernel in one or two buffers while using the rest for subroutine calls. A better algorithm would be least recently used, but was probably to slow. Brian Utterback Intermetrics Inc. 733 Concord Ave. Cambridge MA. 02138. (617) 661-1840 UUCP: {cca!ima,ihnp4}!inmet!ada-uts!brianu LIFE: UCLA!PCS!TELOS!CRAY!I**2