rshepherd@euroies.UUCP (Roger Shepherd INMOS) (02/20/86)
In a recent article Jeff Gortatowsky writes > ..., maybe someone using the INMOS (tm?) transputer (tm ?) > would like to compare the chip two the IBM/Fairchild > alternatives. Since no one else seems to be saying anything about the transputer I thought I would. (I hope I won't get flamed upon for using the net to talk about my employer's products. Anyhow, this is architecturly interesting stuff, not sales hype). Firstly, the transputer is distinguished from other microprocessors in that it is designed for use in concurrent, multi-processor systems. The transputer supports the concurrency model of occam (CSP-like) both within a single transputer and between transputers. The currently available transputer (T414) contains a 32-bit processor, 2k-bytes of RAM , 4 inter-transputer communication links and an external memory interface. The processor is RISC-like in certain ways. The implementation of sequential programs uses only about 35 instructions (all of which have the same format), there are no addressing modes. On the other hand, the processor is micro-coded, and contains complex instructions such as 'input message' or 'start process'. The resulting processor is very small; the chip-size of the T414 is smaller (I think) than the 68020 or 386, and that area is divided between on-chip RAM, communication links and processor. The design of the transputer exploits fast on-chip memory by using only six registers in the execution of a sequential program. The six registers are, . the workspace pointer . the instruction pointer . the operand register (used in the formation of instruction operands) . the A, B and C registers which form an evaluation stack and are the sources and destinations for most arithmetical and logical operations. Loading a value into the stack pushes B into C, and A into B, before loading A. Storing a value from A, pops B into A and C into B. Expressions (and addresses) are evaluated on the evaluation stack, and instructions refer to the stack implicitly. For example, the 'add' instruction adds the top two values in the stack and places the result on the top of the stack. The instruction set was designed to be compiled to. (It was assumed that an assembler would NOT be used). It contains a relatively small number of instructions chosen to give a compact representation of the operations most frequently occuring in programs. Each instruction consists of a single byte divided into two 4 bit parts. The 4 most significant bits are a function code, and the 4 least significant bits a data value. This representation provides 16 functions, each with a data value ranging from 0 to 15. Thirteen of these are used to encode the most important functions performed by any computer. The 'load constant' instruction enables values between 0 and 15 to be loaded with a single byte instruction. The 'load local' and 'store local' instructions access locations in memory relative to the workspace pointer. The first 16 locations can be accessed using a single byte instruction. The 'load non-local' and 'store non-local' instructions behave similarly, except that they access locations in memory relative to the A register. Short sequences of these instructions allow efficient access to data structures, and provide for simple implementations of the static links or displays. Two more of the function codes are used to allow the operand of any instruction to be extended in length. Operands can be extended to any length by a sequence of prefix instructions. In particular, operands in the range -256 to 255 can be represented using one prefix instruction. So, for example, to load the constant value 17 (= #11), the instruction sequence prefix 1 load constant 1 would be executed (2 bytes). The remaining function code, 'operate', causes its operand to be interpreted as an operation on the values held in the evaluation stack. This allows 16 such operations to be encoded in a single byte. However, the prefix instructions can be used to extend the operand of an 'operate' instruction just like any other. The instruction representation therefore provides for an indefinite number of operations. Should anyone want to know more about the architecture than I give here, the best introduction is "The transputer implementation of occam" by David May and Roger Shepherd, in the proceedings of the Fifth Generation Computer Systems Conference, Tokyo, 1984. Otherwise various INMOS literature is available (INMOS Ltd's address and phone number are below and INMOS Corp. is at PO Box 16000, Colorado Springs, CO 80935, USA, phone (303) 630 4000. -- Roger Shepherd, INMOS Ltd, Whitefriars, Lewins Mead, Bristol, BS1 2NP, UK Tel: +44 272 290861 UUCP: ...!mcvax!euroies!rshepherd