johnl@ima.UUCP (John R. Levine) (03/06/86)
The PDP-5, the architecturally compatible predecessor of the PDP-8, was by any
definition the first RISC design. The following is based liberally upon
information from "Computer Engineering" by Bell, Mudge, and Macnamara.
At the time, which was about 1963, DEC was building the 18-bit PDP-4, which
was a souped down and cheaper version of the 18-bit PDP-1. They were also
familiar with the Lincoln Labs LINC, a 12 bit machine designed for laboratory
use, and the machine that brought us DECtape -- a cheap block addressable
medium which was in a sense a very floppy disk conveniently wound on a spool.
DEC was thinking about a machine to use as a front end for a PDP-4 application
to replace some complicated analog equipment. The machine they designed was
the PDP-5, which was reimplemented a few years later as the PDP-8. So their
goal was an honorable RISC one, design it fast and build it cheap.
The PDP-8 had an instruction set pared down to a minimum.
Op code mnemonic use
0 AND logical and accumulator with memory
1 TAD add memory to accumulator (T for twos-complement)
2 ISZ increment accumulator, skip next instr if zero
3 DCA deposit accumulator in memory, clear accumulator
4 JMS jump to subroutine and store return address
5 JMP jump
6 IOT various I/O instructions
7 OPR various accumulator operations and tests
They left out anything they could get away without. For example, they left
out a load instruction because you could get the effect of one by adding a
memory location to a zeroed accumulator. (That's why DCA cleared after it
stored, the next instruction was usually a TAD used as a load.) No subtract
instruction - negate the accumulator (using an instruction suggestively named
CIA) and add. And so forth. The ISZ instruction was important because, with
only one register, you're pretty much forced to keep your loop counter in
core. The 8 was a fun machine to program, particularly from the panel
switches, because of the way you synthesized complex operations from simple
ones, and because it was easy to memorize the entire instruction set. Ten
years later, I still remember practically all of it.
The PDP-8 was the first computer priced under $20,000 and was extremely
sucessful by the standards of anybody but IBM. (I think that IBM sold about
as many 360/30s as DEC did original PDP-8s, but as the 8 was reimplemented 10
times at increasingly low price, it pulled ahead.)
An interesting side note is that the logic design of the 5 was done by Ed
DeCastro. He later had a sixteen bit design that DEC rejected in favor of
Bell's PDP-11. So DeCastro quit and started his own company to build his 16
bit box, the Data General Nova, which didn't do too bad, either. It also had
its RISC-like aspects, notably a load/store architecture and single cycle
arithmetic instructions. Then, of course, they wrapped the Eclipse around the
Nova's instruction set (in its holes, actually) and then the MV/8000 around
that, becoming CISCs with a vengeance with instructions like "do polynomial
approximation of a cosine and then return from subroutine."
--
John Levine, Javelin Software, Cambridge MA 617-494-1400
{ decvax | harvard | think | ihnp4 | cbosgd }!ima!johnl, Levine@YALE.ARPA
The opinions above are solely those of a 12 year old hacker who has broken
into my account, and not those of my employer or any other organization.nather@utastro.UUCP (Ed Nather) (03/06/86)
In article <143@ima.UUCP>, johnl@ima.UUCP (John R. Levine) writes: > The PDP-5, the architecturally compatible predecessor of the PDP-8, was by any > definition the first RISC design. [ ... ] They were also > familiar with the Lincoln Labs LINC, a 12 bit machine designed for laboratory > use, and the machine that brought us DECtape -- a cheap block addressable > medium which was in a sense a very floppy disk conveniently wound on a spool. ...which was, by any definition, the first RISC computer, since it had the same instruction set as the later DEC machines. It was designed at Lincoln Labs by Wesley A. Clark, inventor of the first Average Response Computer, and of the phrases "self-organizing systems" and "intelligent terminals" among many others. He got DEC to produce the boards for his Laboratory Instrument Computer (LINC) which users themselves were to assemble, to save cost. It had a whopping 1K words of memory (12 bits each) and had autoindexing registers in memory, mostly because Clark ran out of bits in the instruction word, and had to leave out the "uppit bit" which was to auto-increment addresses to effect indexing operations. > The PDP-8 had an instruction set pared down to a minimum. > > Op code mnemonic use > 0 AND logical and accumulator with memory > 1 TAD add memory to accumulator (T for twos-complement) > 2 ISZ increment accumulator, skip next instr if zero I'm pretty sure this incremented a memory address, not the accumulator. > 3 DCA deposit accumulator in memory, clear accumulator > 4 JMS jump to subroutine and store return address > 5 JMP jump > 6 IOT various I/O instructions > 7 OPR various accumulator operations and tests > > An interesting side note is that the logic design of the 5 was done by Ed > DeCastro. He later had a sixteen bit design that DEC rejected in favor of I believe he left DEC first, founded Data General, did well, and goaded DEC into coming out with the PDP-11 as an answer to the Nova. DEC, I'm told, rejected the 16-bit design because it was not instruction-compatible with the PDP-8. DeCastro made the same blunder by demanding that the Eclipse et. seq. be backward-compatible with the Novae, so the original, clean instruction set design is now a pile of garbage. The nova arithmetic system consists entirely of combinations of three basic operations in triple-sequence: negate, add, and increment: neg add incr Operation 0 0 0 NOP 0 0 1 INCrement 0 1 0 ADD 0 1 1 AND (preempted because add, incr not useful) 1 0 0 NEGate 1 0 1 COMplement 1 1 0 ADC (add complement) 1 1 1 SUBtract In actual implementation, the coding for the negate operation was inverted but the logic is unchanged. I find this elegant -- and RISCy. This set of operations is just one step of the five (5) sequential operations available in a SINGLE INSTRUCTION on the Nova computers. (The others allow the carry bit to be pre-set, the result of the operation shifted left or right 1 bit, the result tested (skip next instruction if ...) and, finally, the operation's result re-loaded into the target register or discarded. While I can see the problem compiler-writers have with a system like this, a careful assembly-larguage programmer can write fast, short code for some surprisingly complicated operations. In the infamous "sieve" benchmark the operation I + I + 3 in the inner loop can be done in a single Nova instruction. "What do you mean? These *are* the Good Old Days!" -- Ed Nather Astronomy Dept, U of Texas @ Austin {allegra,ihnp4}!{noao,ut-sally}!utastro!nather nather@astro.UTEXAS.EDU