gnu@hoptoad.uucp (John Gilmore) (03/18/86)
The quoted article seems to be full of errors. In article <777@harvard.UUCP>, reiter@harvard.UUCP (Ehud Reiter) writes: > 2) Complex instruction execution - the following figures compare a > "VLSI VAX" (presumable a microVAX), an M68020 (16 Mhz, no wait states), and > an IBM PC/RT, all executing the operation R3=4(R2)+(R1). > uVAX 68020 real-RT cache-RT > time (us) 1.2 .94 1.83 .83 > cycles 6 15 11 5 > bytes 5 6 6 6 > cycle time (ns) 200 60 170 170 > instructions 1 2 3 3 > scratch registers 0 0 1 1 I don't know the other instruction sets, but the 68020 could use "lea 0(a1,d2*4),a3" for 3 to 6 cycles, 4 bytes, and 1 instruction, reducing the time to .18 to .36 usec. Of course, this only works when one source and the destination are address registers, but this is reasonable since the calculation being performed looks suspiciously like subscript calculation. I can't find a 2-instruction sequence that would do this operation for three data registers. > 3) Simple instruction execution - for R3=R1+R2 > uVAX 68020 RT > time(us) .4 .25 .17 > cycles 2 4 1 > bytes 3 2 2 > instructions 1 1 1 I don't know a 68020 instruction that does this. The 68000 series has few if any 3-operand instructions unless you synthesize them from the addressing modes as I did above. --- Maybe the author doesn't know the 68020 but in that case he should refrain from comparing it to the other machines. My inclination is to not trust any of the figures. -- John Gilmore {sun,ptsfa,lll-crg,ihnp4}!hoptoad!gnu jgilmore@lll-crg.arpa Post no bills.
reiter@harvard.UUCP (Ehud Reiter) (03/19/86)
In article <634@hoptoad.uucp> gnu@hoptoad.uucp (John Gilmore) writes: > >In article <777@harvard.UUCP>, reiter@harvard.UUCP (Ehud Reiter) writes: >> 2) Complex instruction execution - the following figures compare a >> "VLSI VAX" (presumable a microVAX), an M68020 (16 Mhz, no wait states), and >> an IBM PC/RT, all executing the operation R3=4(R2)+(R1). > >I don't know the other instruction sets, but the 68020 could use >"lea 0(a1,d2*4),a3" for 3 to 6 cycles, 4 bytes, and 1 instruction, The operation is R3=4(R2)+(R1) (that is, adding the memory word whose address is R2+4 to the memory word pointed to by R1 and storing the result in R3), not R3=(R1+4*R2), which is what Mr. Gilmore seems to think. I would have preferred to give data on a more common CISC instruction, but the above is the only one I have VAX data for. >> 3) Simple instruction execution - for R3=R1+R2 > >I don't know a 68020 instruction that does this. The 68000 series >has few if any 3-operand instructions ... You're absolutely right. The figures are for R1=R1+R2 - sorry for the typo. In the future, if someone thinks he has found a factual mistake in a posting of mine, I would appreciate it if he would tell me about it first, so that simple misunderstandings (as seems to be the case with Mr. Gilmore) do not clutter up the net. Thanks. Ehud Reiter harvard!reiter.UUCP reiter@harvard.UUCP