[net.arch] risc questions really, smart I cache from ancient history

ken@turtlevax.UUCP (Ken Turkowski) (04/07/86)

In article <208@valid.UUCP> gelfand@valid.UUCP (Brooks Gelfand) writes:
>The Motorola 68010 has a loop mode operation that works with the
>DBcc instruction. In this case the loop is only one instruction deep.

There are even further restrictions; you can do a block copy
	L:	movl a0@+,a1@+
	dbra	d7,L
but you can't poll an I/O device's busy bit
	M:	btst #3,a0@
	dbeq	d7,M
and still remain within the cache.

Does anybody know why Motorola doesn't allow just any instruction
that will fit?
-- 
Ken Turkowski @ CIMLINC, Menlo Park, CA
UUCP: {amd,decwrl,hplabs,seismo}!turtlevax!ken
ARPA: turtlevax!ken@DECWRL.DEC.COM