hansen@mips.UUCP (04/22/86)
> > How do you make sure that, whenever you re-use a process-id, all old > > data is flushed from the cache? > > This problem comes up in almost any cache environment; the answer is that > you need some form of selective flushing. The only exception is if the > cache is caching physical addresses *and* sees all i/o activity (say, > by watching the bus) so that memory data can't change underfoot. Note > that this applies both to data/instruction caches and to TLBs, which > are just specialized caches. > > The process-ids found in caches generally are fairly short, on the > assumption that processor activity shows fair locality in the process-id > space. Examples are the MIPS TLB (six bits of pid, I think it was) and > the ISI and SUN 68020 MMUs (three bits of pid). > -- > Support the International > League For The Derision Henry Spencer @ U of Toronto Zoology > Of User-Friendliness! {allegra,ihnp4,decvax,pyramid}!utzoo!henry I just wanted to clarify that while the MIPS R2000 TLB contains six bits of process-id, the caches are entirely physical. Thus, when a pid must be reused, the TLB must be flushed, but the cache need not be flushed. As to whether the flushing should be selective or not, let me suggest that selective flushing will only free up a single pid, while a wholesale flush will free up all pids. (And a non-selective flush is usually faster, too.) Of course, in counting the performance effect, you should take into account the time required to refill the TLB and/or cache with useful data again. Note that flushing a TLB is less expensive than flushing a cache. -- Craig Hansen | "Evahthun' tastes MIPS Computer Systems | bettah when it ...decwrl!mips!hansen | sits on a RISC"
steve@gondor.UUCP (Stephen J. Williams) (04/23/86)
>> How do you make sure that, whenever you re-use a process-id, all old >> data is flushed from the cache? Do this with the paging system. Get a page fault for a page that was not yet accessed by this page, and you give it a clean page. --Scal