aglew@ccvaxa.UUCP (04/22/86)
Another attempt to make life interesting: How would you react to an instruction set that had no indexed addressing mode, but did have a mode where a register was ORed into the address? I can vaguely recall having seen such a beast - is anyone familiar with it? I laughed then, but now I can see arguments for providing such an ORed index addressing mode, in the lack of true indexing. First off, ABSOLUTE and REGISTER INDIRECT are a logically sufficient set of addressing modes. You don't really need indexing. You might want to get rid of indexing because it requires an addition, which requires carry propagation, which slows up the basic memory access cycle, even though ABSOLUTE and REGISTER INDIRECT don't need the add. Now, indexing is used in two distinct ways: accessing arrays, and accessing fields in structures. Losing indexing for array accesses isn't too bad, since just about every expensive array operation can be written using pointers instead of indexes (post-increment doesn't require a carry to perform a memory address). Access to fields in structures, however, doesn't suit pointer arithmetic quite so nicely, since it is much more random. And structures are VERY important in an operating system like UNIX. So what can you do? Adding an index register in slows down the rest of your instruction set, but you do want a way to offset a short distance from a pointer to form the address of a field in a struct, without incurring a large carry delay. Well, you can always just stop the carry from propagating past a certain point. Don't we all love the 8086? Actually, it's not that bad - pointers can be an arbitrary size, you'd just have to ensure that no structure overlaps the segment boundary determined by the point at which you stop propagating the carry. `calloc' can do that. The other option would be to use a carry-less function like OR. ORed indexes would only really be useful for structures that are a power of two in size, but there are a lot of those - and, if memory is cheap, you might be willing to pad out a lot more of your structures, to get a speed increase. Well, there you have it: ORed indexes. Tell me I'm brain damaged. Andy "Krazy" Glew. Gould CSD-Urbana. USEnet: ihnp4!uiucdcs!ccvaxa!aglew 1101 E. University, Urbana, IL 61801 ARPAnet: aglew@gswd-vms
knudsen@ihwpt.UUCP (mike knudsen) (04/22/86)
> How would you react to an instruction set that had no indexed addressing > mode, but did have a mode where a register was ORed into the address? > > Well, there you have it: ORed indexes. Tell me I'm brain damaged. > > Andy "Krazy" Glew. Gould CSD-Urbana. USEnet: ihnp4!uiucdcs!ccvaxa!aglew > 1101 E. University, Urbana, IL 61801 ARPAnet: aglew@gswd-vms Nah, your brain is OK. I built a special-purpose (but sorta general architecture) computer out of STTL to run at 10 MHz about 5 years ago. Each instruction completes in 100 nsec, for you RISC freaks. No branching or access delays are needed, tho each memory write overlaps with the next instruction's decode. It controls 64 identical hardware items, so there are several arrays of 64 words each. So YES, I do OR'ed indexing. The low 6 bits of my pointer registers are ORed with constant bases which select which array gets accessed. (This is just the reverse of structure fields, where constant offsets are added to *big* pointers.) Actually, all 12 of my index bits are significant. This allows 128, 256, ... -word arrays if they are aligned on the proper boundaries. Also my assembler for the machine supports "free-basing" where the ORed base is zero so the index accesses the whole 4K of RAM randomly. (My term free-basing has since been expropriated, but I claim Pryority in the matter. The 3 boards get hot as Hades but have never caught fire, or even failed in 4 years of operation.) mike k
kludge@gitpyr.UUCP (Scott Dorsey) (04/24/86)
In article <5100066@ccvaxa> aglew@ccvaxa.UUCP writes: > >How would you react to an instruction set that had no indexed addressing >mode, but did have a mode where a register was ORed into the address? Cute. I like it. From the looks of it, this would make record types easy to implement. It sounds familiar.. I have seen it on one of the newer 32-bit processors in addition to indexed addressing. It wouldn't replace indexing too well except maybe on a machine with a slow add. Newer boxes often have an adder seperate from the ALU to handle indexing which takes so little time to do the calculation that such a scheme really wouldn't make all that much sense as an indexed replacement. This is not to say that I wouldn't like it; how about two registers, one added, then the other or'ed. -- ------- Disclaimer: Everything I say is probably a trademark of someone. But don't worry, I probably don't know what I'm talking about. Scott Dorsey " If value corrupts kaptain_kludge then absolute value corrupts absolutely" ICS Programming Lab (Where old terminals go to die), Rich 110, Georgia Institute of Technology, Box 36681, Atlanta, Georgia 30332 ...!{akgua,allegra,amd,hplabs,ihnp4,seismo,ut-ngp}!gatech!gitpyr!kludge
philm%astroatc@astroatc.UUCP (04/27/86)
In article <5100066@ccvaxa> aglew@ccvaxa.UUCP writes: > >Another attempt to make life interesting: > >How would you react to an instruction set that had no indexed addressing >mode, but did have a mode where a register was ORed into the address? > >I can vaguely recall having seen such a beast - is anyone familiar with it? >I laughed then, but now I can see arguments for providing such an ORed index >addressing mode, in the lack of true indexing. > . . . . . . . > >Well, there you have it: ORed indexes. Tell me I'm brain damaged. > >Andy "Krazy" Glew. Gould CSD-Urbana. USEnet: ihnp4!uiucdcs!ccvaxa!aglew >1101 E. University, Urbana, IL 61801 ARPAnet: aglew@gswd-vms The PERQ workstation has OR'd indexing for its register file. The PERQ was one of the first workstations on the market. It is a 2910/Custom ALU microengine with barrel shifter and Raster-Op. -- =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Kirk : Bones ? Phil Mason, Astronautics Technical Center Bones : He's dead Jim. {Your Favorite System}!uwvax!astroatc!philm My opinions are mine and not necessarily those of my employer. (I would like to think that my employer believes in them too.) :-) =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
mac%uvacs@uvacs.UUCP (04/30/86)
> How would you react to an instruction set that had no indexed addressing > mode, but did have a mode where a register was ORed into the address? > > I can vaguely recall having seen such a beast - is anyone familiar with it? IBM 7090? 3-bit index register field, 3 index registers. I believe the registers selected were OR'd together, then ADDed to the offset. > .... Losing indexing for array accesses isn't too bad, since > just about every expensive array operation can be written using > pointers instead of indexes (post-increment doesn't require a > carry to perform a memory address). No semi-random access by subscripts? Your machine is to be programmed exclusively in C or assembler, never Fortran. > So what can you do? Adding an index register in slows down the rest of your > instruction set, Even when you don't index? > .... and, if memory is cheap, you might be willing to pad out a > lot more of your structures, to get a speed increase. or use a separate add instruction.
johnl@ima.UUCP (John R. Levine) (05/03/86)
In article <5100066@ccvaxa> aglew@ccvaxa.UUCP writes: >How would you react to an instruction set that had no indexed addressing >mode, but did have a mode where a register was ORed into the address? OR'ed indexes, eh? Back in olden days, the IBM 704, 709 (tubes), and 7040 and 7090 (transistors) each had 3 index registers, numbered 1, 2, and 4. Normally, if you specified one index register, it was subtracted in twos complement from the base address in the instruction. (Why subtracted rather than added is something I never understood, particularly since they were subtracted twos-comp and the machine was otherwise sign-magnitude. But I digress.) If you set more than one of the three bits in the index register field, the corresponding registers were or'ed together before they were subtracted from the base address. Sounds handy, no? Well, no. It was completely useless and probably due to a random wiring peculiarity in the 704. In the 7094, there were 7 different index registers and specifying register 6 got you register 6 rather than registers 2 and 4 or'ed. I gather that almost every 7090 program worked on the 7094, which means that nobody used the or'ing. Pfui. -- John R. Levine, {ihnp4 | decvax | cbosgd | harvard | yale }!ima!johnl Levine@YALE.EDU The opinions expressed above are those of a 12-year-old hacker who has broken into my account and not those of any person or organization.
tp@ndm20 (05/11/86)
>digress.) If you set more than one of the three bits in the index register >field, the corresponding registers were or'ed together before they were >subtracted from the base address. Sounds handy, no? Well, no. It was >that almost every 7090 program worked on the 7094, which means that nobody >used the or'ing. Pfui. The Harris H-series (24 bit architecture, proprietary OS) has a similar wierdness. SOME instructions allow exactly what is described above, but not in indexing, these are direct register references. These are machines that are around today. I doubt anyone uses the feature, since the assembler doesn't give you a way to set multiple bits (not documented anyway). In some cases it would be nice. You could or registers on a move operation, thus saving several or instructions. Terry Poot Nathan D. Maier Consulting Engineers (214)739-4741 Usenet: {seismo!c1east | cbosgd!sun | ihnp4}!convex!infoswx!ndm20!tp CSNET: ndm20!tp@smu ARPA: ndm20!tp%smu@csnet-relay.ARPA