hes@ecsvax.UUCP (Henry Schaffer) (04/30/86)
<>I have read about the new Vector Extension of the Intel Personal Supercomputer. This adds a vector processor to each of the processing nodes. (The iPSC is a commercial implementation of the "hypercube" idea.) (In Mgmt. Info. Syst. Week, Apr 21, p 8). If you add the VX to a /d6 (six dimensional hypercube = 64 nodes) it costs $850,000 instead of $280,000. It then has an (aggregate) performance level of ~200 Mflops. (For /d5 or /d7 use a factor of 2 to get approx. values for all the preceding numbers.) Upgrades are available for non-VX machines. The VX series is supposed to offer speeds of a Cray X-MP. (Serlin of Itom Int'l said, "Think of it this way. You cannot lash four Volkswagens together and suggest that they will equal the performance of a Porsche.") Does anyone know anything more about the vector processing architecture of this series? --henry schaffer ...!mcnc!ecsvax!hes
brooks%lll-crg@lll-crg.UUCP (05/04/86)
In article <1502@ecsvax.UUCP> hes@ecsvax.UUCP (Henry Schaffer) writes: ><>I have read about the new Vector Extension of the Intel Personal >Supercomputer. This adds a vector processor to each of the processing >nodes. (The iPSC is a commercial implementation of the "hypercube" >idea.) (In Mgmt. Info. Syst. Week, Apr 21, p 8). The vector processing option replaces half of the boards in your machine, you pull out every other processor board and plug these vector boards in. The vector board looks like a chunk of memory to the processor its connected to. It has a microcode control store area on it and weitek floating point chips do the work. The operation of the floating point processor looks like subroutine calls to the node cpu its hooked to. The single most worrysome problem is that the communication performance is not inproved. The communication performance is already marginal, for short messages, and the factor of 10 to 100 speed improvement for floating point will make communication performance only look that much worse. There are applications for which it wont matter, but there are also problems for which it will be critical.
moler@intelisc.UUCP (Cleve Moler) (05/14/86)
Concerning our Intel iPSC-VX hypercube with vector boards, Eugene Brooks writes, in part: > The vector processing option replaces half of the boards in your machine, > you pull out every other processor board and plug these vector boards in. > ... It has a microcode control store area on it and weitek floating point > chips do the work. ... The single most worrysome problem is that the > communication performance is not improved. ... There are applications for > which it won't matter, but there are also problems for which it will be > critical. The chips are NOT from Weitek, but rather from Analog Devices. They're competitors for the Weitek chips, but they're CMOS and so use much less power -- a vital consideration when you are using up to 128 of them in a system. (64 floating point adders and 64 multipliers in a 6 dimensional hypercube.) We expect the peak floating point performance per board to range from 3.3 megaflops for 64-bit memory-to-memory operations to 20 megaflops for 32-bit register-to-register tight loops. A system contains 16, 32 or 64 boards, so the total performance could range from 50 to 1280 megaflops, IF we can keep all the boards busy all the time. Brooks is right that the node-to-node communication performance can be quite important. For many large scale scientific calculations involving matrices and partial differential equations, especially three dimensional PDEs, there is so much arithmetic to be done that it is possible to partion the problem across the nodes in ways that make communication time negligible. Of course, we are continuing to make improvements in both software and hardware, and communication times are a high priority. (It will soon be possible to also run Caltech's Crystalline system, which Brooks developed, on our VX system. This will be an alternative way to improve communication times for short message to direct hypercube neighbors.) --Cleve Moler, Applications Research Manager Intel Scientific Computers