rb@cci632.UUCP (Rex Ballard) (07/25/86)
In article <496@elmgate.UUCP> jdg@elmgate.UUCP (Jeff Gortatowsky) writes: >In article <136@mipos3.UUCP>, kds@mipos3.UUCP (Ken Shoemaker ~) writes: >> And my last word, my firm belief is that any processor designed without >> any (or a very small) consideration to either the software that the >> thing is going to run, OR the hardware implementation that is required >> to execute the instructions is doomed to failure. And this includes >> processors that are designed by compiler writers living in a vacuum. >> -- >> The above views are personal. >> Ken Shoemaker, Microprocessor Design, Intel Corp., Santa Clara, California > >First a tongue-in-cheek remark to Ken on the above paragraph: >Where the heck were you when they were designing the 8088/86/186/286, hmmm? > >Second a completely different topic: >Ken, with the success of the PC's, how much outside influence (if any) did >certain large(!) computer makers have on the design of the 386? > >To everyone: >Does anyone know of a successful or failed CPU design that was >significantly changed or built from scratch, because of outside influence? According to the folklore: Motorola, in designing both the 6809 and the 68000, surveyed many of it's own customers, AND non-customers before proceeding with designs for their "next generation" chips. Intel seems to have focused more on the "system" as a whole, by adding the DMA, interrupt controller, etc. on chip. Ironically, Phillips is following the "system on a chip" lead, but with the 68K instruction set. Except for really "innovative" (like Berkely RISC) designs, I would guess that most commercial manufacturers do some heavy market research before they "commit to silicon". Hopefully, chip makers will broaden their scope of market research a little more, and combine the best of "system on a chip" with "compiler/programmer friendliness". To be fair to Intel, 1 meg was an enormous memory map compared to the 64K predecessors. 16bit registers were also quite attractive compared to a 6502, 8080, Z-80, or 8085. The 68K was difficult to support because it was such a radical departure. Motorola took a long time to come up with a VM MMU, and most of the "Support chips" to build a complete system at a competitive price. They also took too long to support 8-bit data-busses. This isn't as significant now, but when you needed 16 chips to get 128K and 4 bit Drams weren't available, the 68K was an expensive proposition.
bryant@oakhill.UUCP (Bryant Wilder) (07/27/86)
here are some comments on the postings i've seen lately in net.arch on outside influences on chip design, specifically on the posting by rex ballard, 260@cci632.UUCP. >according to the folklore: >Motorola, in designing both the 6809 and 68000, surveyed many of its >own customers AND non-customers before proceeding with designs for their >"next generation" chips. i'm going to write about the outside influences on the definitions of the MC6809, the MC68000, and the DSP56000 chip designs. i was the project leader on the 6809 so i know exactly what happened on that chip design. terry ritter, chief architect, spent a lot of time on the road asking customers what they liked and didn't like about the 6800 and other chips on the market. terry like all architects had a lot of ideas that he was pushing (sometimes slugging) for the 6809. in general he wanted the 6809 to be a machine that made sense to a programmer. there was an incredible amount of discussion both internally and with customers about whether to include the DPR, direct page register. the DPR is in the 6809 and i hope the customers like it. customers are directly responsible for the FIRQ, fast interrupt. i have heard from many customers that they love it. terry pushed it, but customer input is responsible for its inclusion. i don't know where terry came up with the idea-customer, himself, or the 68000 team-but one day he wanted to do an instruction called PEA, push effective address. my reaction like any circuit design guy in the middle of a project was it is too late now to change the flow chart and logic. the instruction looked good from a customer point of view so i looked at how to do it for a few days. i told terry that PEA was not possible but load effective address, LEA, could be implemented. he went off for a few days to do something (think or talk to customers or what) and came back beaming that LEA was even better. that's how that instruction happened. for those of you who may wonder why the 6809 has only a 64K addressing space, that is because terry said in meeting after meeting that everyone he talked to thought memory was going to remain expensive and 64K was about all anyone was willing to afford for an 8 bit processor. i guess architects and customers cannot anticipate everything. :-) in summary the 6809 was an architects dream bounced off internal and external customers and we did change the design using customer input. i think i know a good deal about how the 68000 architecture was done, and i talked to tom gunther today, 7/26/86, about it. in 1976 tom kept talking to me about a project he wanted to do called MACS, Motorola Advanced Computer System, which would be at least 10 times the performance of the 6800. at some point he convinced colin crook that it should be done and in january, 1977, tom moved out of F building to an isolated V building to work in isolation. i visited him occassionally and it looked like he was doing a lot of reading. tom told me that colin did whatever customer contact was made. at some point skip stritter and nick tredenick (try copying this guy's signature sometime) joined tom's group, and as tom puts it, "we played architecture class everyday." tom's input to me was, "we were young and naive" and we just defined the 68000 the way we wanted. the 68000 was a pretty secret project and not many customers were contacted. from what i know about the 68000 design-ins and the 68020 design-ins, it looks like tom and crew did pretty well!! i have been the operations manager for the Motorola DSP business unit since its start so i know how the DSP56000 architecture happened. we went through several large and time consuming iterations of architectural specifications and we talked to many customers. we wanted to design a dsp chip that has lots of speed, lots of parallelism, an instruction set that dsp guys can use, lots of on chip peripherals to interface to chips that dsp/fast controller guys use, and we wanted to make pipelining invisible so the software guys wouldn't break their heads programming the chip. we also wanted a design that could support garden variety high level languages. when we started the design, risc was not so in vogue. if one looks at the chip, one will see that it is a "kinda risc machine" with lots of parallelism ( three execution units operating simultaneously) with lots of on chip peripherals. we made many, many changes to the design based on customer inputs. since we went public last march, the customer response to the chip has been very enthusiastic. several motorola salespeople have told me no chip that motorola has announced has ever gotten this much customer interest--not even the 68000 or 68020. in summary the DSP56000 was designed with a great deal of customer/outside input. if any of you are familiar with the DSP56000 and you want to see some improvements made to it, we want to hear from you! bryant wilder {seismo,ihnp4,gatech,harvard}!ut-sally!oakhill!bryant (512) 440-2033 or sun!oakhill!bryant