shep@datacube.UUCP (08/07/86)
Thanks for the post of the DSP56200. It is good to be able to read of new DSP chip architectures here in net.arch. I assume that the DSP56200 is designed as a peripheral for the 56000. Table 1, listing the DSP56200 "performance figures" did not make any sense: It seems for a FIR filter application with, say, 32 taps, the maximum sampling frequency DECREASES as you add chips. This doesn't make any sense. Can anyone explain or correct? A more convenient way I've found to express the compute power of a FIR filter chip/board/system is to express the performance in time/point . This allows filter aperture and sample rate to vary whilst the hardware remains fixed: For example: We recently designed a VMEbus module that performs a 64 point FIR filter on a 10 MHz sample train in one or two dimensions. By expressing the board's performance simply as 1.56 nS/point, it is a simple matter to trade off aperture vs. sample rate conceptually. Of course, there are often underlying issues that must also be taken into consideration; but this gets you close! Shep Siegel UUCP: [ihnp4 | mirror]!datacube!shep Datacube Inc.; 4 Dearborn Rd.; Peabody, Ma. 01960; 617 535 6644