[net.arch] Dual Port Memory

nader@ut-ngp.UUCP (Nader Bagherzadeh) (08/23/86)

I need some information on Dual Port Memories (DPM).  Is it possible to
improve the bandwidth by using DPMs or it is just a technology 
improvement to hide the arbitration in the memory.  That is given a 
current technology, if the the single port memory has bandwidth 
BW can I expect to get a better performance that BW/2 at each input 
of the DPM (assuming fair arbitration).

Please postnews or send direct e-mail to nader@ngp

University of Texas at Austin
Elect. Comp. Eng.

philip@amdcad.UUCP (Philip Freidin) (08/26/86)

In article <3866@ut-ngp.UUCP>, nader@ut-ngp.UUCP (Nader Bagherzadeh) writes:
> I need some information on Dual Port Memories (DPM).  Is it possible to
> improve the bandwidth by using DPMs or it is just a technology 
> improvement to hide the arbitration in the memory.  That is given a 
> current technology, if the the single port memory has bandwidth 
> BW can I expect to get a better performance that BW/2 at each input 
> of the DPM (assuming fair arbitration).

	It depends on your definition of what a dual (or tripple or quad...)
port memory is.  (little comercial here) At AMD we make several memory type
devices for our 2900 family of bitslice and microcodeable processors. These
memories are usually refered to as true dual-port, because there is no
arbitration involved. For each port, there is an address path, as well as a
data path. If the access time is 20nS, then on a dual ported part you can
do 2 reads in 20nS. We usually call these types of parts Register files 
because they are usually connected directly to the data paths around the ALU.
We also make a four port register file for the 29300 family, but we do some
games with the address and clock signals to get there.  Even so, the BW is
greater than 2.0 * the BW of 1 port. We also make a 1k byte dual port chip
as the Am2130. This part gives ou 2.0 * BW, except if both ports access the
same location.  In this case the contention logic will issue a busy signal
to the loser.
In system memories, it is not uncommon to find memory cards that are dual
ported. One port directly to the CPU, the other to the main peripheral bus.
In this type of environment, the major advantage is overlapping of bus
arbitration (on the peripheral bus), with transfers to the CPU. (see the
Intel Multibus spec, with the P1 bus as the peripheral bus, and the P2 bus
as the CPU link.  they call is iLBX).  The memory chips on these types of cards
are standard DRAMs, and as such, they can only do one transfer at a time.
			Hope this is helpfull,
			Hope not too many people find it controversial
			Philip Freidin.