awpaeth@watcgl.UUCP (Alan W. Paeth) (08/29/86)
With regards to Shein's law (zeroing memory in N seconds):
I heard DEC's VP of research, C. Gordon Bell while at Caltech in 1976. As part
of his guest lecture (discussing PDP11 architecture), he commented that a
memory which cycled in 1uS gave rise to 1 Meg as a reasonable upper bound for
storage, with memory size and access time trading off in direct proportion
for other values. Ivan Sutherland (CS chairman at the time) then proposed
that a maxim for good design was "being able to initialize memory in one
second", and Bell agreed. This is really a bandwidth measure, as the memory
is presumably filled via DMA, if it is to run at its full bandwidth. It is
useful as a measure of CPU speed assuming that the CPU cycles at rates
comparable to the main memory cycle time (which may not be true with
architectures with huge memories a/o multiprocessors). This could account for
a factor of N on newer designs.
/Alan Paeth, University of Waterloo