johnl@ima.UUCP (John R. Levine) (09/14/86)
In article <3608@amdahl.UUCP> mat@amdahl.UUCP (Mike Taylor) writes: >Just a few comments on what the large 370 world does about some of the >problems that have been raised with very large memories. First of all, >large memories in this world are always multi-ported and accessed >through caches. ... The latest issue of the IBM Systems Journal (known affectionately as "Pravda") is about the new 3090 series. I was amazed to learn that in the four-processor version, the processors are set up in pairs, with half of the memory attached to each pair. If a processor wants to get to memory attached to the other pair, it has to ask the other side to get it. They have large write-behind caches, so that the number of memory references is very low compared to the number of instructions executed, but it still seems like a peculiar way to build a memory. >A further simplification is third level mainstore - so-called expanded >store - which is only page-addressable. A whole page is copied in and out >of mainstore at a time. This is really a synchronous paging device - such >an operation only takes about 20 microseconds, though, and saves a lot >of overhead associated with doing an I/O. The IBM articles wrote about this stuff in considerable detail. They claim that making the transfers synchronous is a big win, because the transfer takes less time than a context switch so there's no time to do useful work anyway. Interrupt latency seems not to be a concern because the channels are so smart. They also said that the expanded store is addressed by page, so that the expanded store address of 32 bits addressed not 4G bytes but 4G pages or 16TB, so they won't run out of address space this time. Still embarassed about 24-bit addressing, I guess. There are also some articles on the vector instructions which make moderately persuasive arguments that the way that they did it (128-element vector registers, no instruction chaining) was the right way to do it. They did make allowance for making the vector registers larger or smaller power-of-two sizes, which seems forward-looking. -- John R. Levine, Javelin Software Corp., Cambridge MA +1 617 494 1400 { ihnp4 | decvax | cbosgd | harvard | yale }!ima!johnl, Levine@YALE.EDU The opinions expressed herein are solely those of a 12-year-old hacker who has broken into my account and not those of any person or organization.