lamaster@nike.uucp (Hugh LaMaster) (10/28/86)
A question for hardware designers and computer architects on the net:
What instructions actually slow a processor down? While the RISC/CISC
debate has often focused on complexity, chip real estate, etc., there
seem to be cases where the existence of a particular instruction can
slow the processor because of pipelining considerations. Complex
addressing modes are also a question: Are there indirect or complex
addressing modes whose implementation necessarily slows down direct
loads and stores? What is the best example of an existing CISC
machine which does not have any of these "unnecessary" architectural
features or instructions?
Hugh LaMaster, m/s 233-9, UUCP: {seismo,hplabs}!nike!pioneer!lamaster
NASA Ames Research Center ARPA: lamaster@ames-pioneer.arpa
Moffett Field, CA 94035 ARPA: lamaster%pioneer@ames.arpa
Phone: (415)694-6117 ARPA: lamaster@ames.arc.nasa.gov
"He understood the difference between results and excuses."
("Any opinions expressed herein are solely the responsibility of the
author and do not represent the opinions of NASA or the U.S. Government")