henry@utzoo.UUCP (Henry Spencer) (10/28/86)
> > ... the last time I checked, cycle time > > doesn't vary with addressing mode, even on the CISCiest of CISCs... > > Varying cycle time is not uncommon in the PDP11 line, at least in the 11s > I've had cause to investigate in detail. The microcode selects the cycle > time it wants on a cycle-by-cycle basis, presumably with the delays of > different processor sections in mind. Several people have expressed some interest in knowing details, so I think it's probably worth posting this. The best information on this sort of thing is in an old CMU tech report titled "Impact of Implementation Design Tradeoffs on Performance: The PDP-11, A Case Study", by Snow and Siewiorek. It's long out of print, but is reprinted in Bell, Mudge, & McNamara's "Computer Engineering" book. The report is too old to cover the newest 11s. I would guess that varying cycle times are rather less likely in the LSI implementations, which would let out the 23, 24, 73, 84, and the T11 and J11 chips. The only other 11 that I can think of which is too new to be covered is the 44, the last of the MSI implementations. The 44 does have two different cycle times, although a quick glance at the processor manual doesn't tell me exactly what it uses them for. [I can hear cries of "so what does the report say?". Here goes.] Of the older 11s, up to and including the 60, there are three with gearshifts: the 10, 34, and 40. The 11/10 doubles its clock speed for doing multi-bit shifts. This may seem a bit specialized, especially when you remember that the 10 has no multi- bit shift instructions! The key thing to remember is that the 10 was a bare-minimum-cost 11 designed circa 1970, when the variety of MSI chips was limited. So the 11/10 does not have a byte swapper. When it wants to get at an odd-numbered byte, it has to do an 8-bit shift. This may sound like a gross performance disaster, but it's not; the report examined the possible performance improvement from adding a byte swapper to the 10, and concluded it would be quite small. Odd-byte accesses simply aren't common. The 11/34 has a long cycle for bus operations and a short cycle for normal activity. The report didn't go into detail. The 11/40 is the fanciest of the lot, with a three-speed gearbox. It uses an extra-long cycle for the worst-case use of the data paths, reading from and writing to scratchpad RAM in the same cycle. The medium cycle is for data-path cycles that don't involve writes to the scratchpad. And the short cycle is for microinstructions which don't use the data paths at all, and hence don't care about their propagation delays. As I recall, the report assessed this multi-speed mechanism as quite effective in speeding up a relatively simple implementation. -- Henry Spencer @ U of Toronto Zoology {allegra,ihnp4,decvax,pyramid}!utzoo!henry