kludge@gitpyr.gatech.EDU (Scott Dorsey) (10/23/86)
Question: What is the effect on the efficiency of an instruction set due to the exchange and conditiona return instructions. Shades of Z-80dom, huh? By exchange I mean either a register-to-register exchange (very fast with two internal busses), not a register-to-memory exchange (slow, unless you have multiple data and address busses :-)), or core-to-core exchanges (impossibly useless). By conditional returns, I mean a return with the same format as the conditional jump. Return on carry would be great, return on parity would not be so useful. I have used these features on several machines and have become quite depressed that they aren't found in may of the current generation of microprocessors.
greg@utcsri.UUCP (Gregory Smith) (11/02/86)
In article <2469@gitpyr.gatech.EDU> kludge@gitpyr.UUCP (Scott Dorsey) writes: >Question: What is the effect on the efficiency of an instruction set due >to the exchange and conditiona return instructions. Shades of Z-80dom, >huh? >By exchange I mean either a register-to-register exchange (very fast >with two internal busses), not a register-to-memory exchange (slow, unless >you have multiple data and address busses :-)), or core-to-core exchanges >(impossibly useless). The Z80 ( like the 8080 ) does a register exchange (DE swaps with HL) in the same time it takes to do a NOP*. If you look at the times for some of the other instructions, it is fairly obvious that there are not a lot of busses in there. I am quite certain this swap is done by 'renaming' the registers rather than swapping the contents. I.e. in LD DE,22 EX DE,HL LD (MEM),HL the memory location 'MEM' is written from the same physical register which was set to 22 in the first instruction. Also consider that you can't change EX DE,HL to EX DE,IX by putting hex DD before the opcode as with most instructions - there is no way to 'swap the names' of IX and DE so it won't work. This renaming is actually done by causing the register_number_decoded_from_opcode -> physical_register mapping to be modified. If you wanted to use this method with, say, a 16-register CPU like the 68K, and allow any swap to be done, the mapping would have to go through a 16x4 ram which would be modified by swap instructions. [not quite -- consider the two SP's, both 'named' A7 at different times]. In this case it is better to move the actual data. The 68K does have an instruction which will swap any reg. pair in {D0-D7,A0-A7}, BTW. The same comments apply to the Z80 EX AF,AF' instruction, and the EXX instruction which 'swaps' three 16-bit regs in no time flat (in Z80 terms :-)) Can anybody with knowledge of the Z80 insides confirm this? *or pretty close, anyway. I can't find my Osborne intro to uP vol II to check. Regarding conditional returns: they are great for hand-coding assembler. However, when using a high-level language, a subroutine return usually requires cleanup code before the actual return, so you are better to branch conditionally to that. If the return instruction does that cleanup, then it may be time-consuming enough that another branch isn't going to hurt. Consider also that the Z80/8080 only has 8 conditions (Z/C/Minus/Parity(!) and their complements) whereas most newer CPUs have 16 -- and having a different set of conditions for RETs and BRAnches would be painful for compilists. I certainly don't consider all of this a strong argument against conditional returns; just giving some reasons why it may not be worth the opcode space. -- ---------------------------------------------------------------------- Greg Smith University of Toronto UUCP: ..utzoo!utcsri!greg Have vAX, will hack...