Info-IBMPC@USC-ISIB.ARPA (10/26/84)
From: Info-IBMPC Digest <Info-IBMPC@USC-ISIB.ARPA> Date: 21-Oct-1984 1807 From: mitton%elrond.DEC@decwrl.ARPA (Dave Mitton) To: info-ibmpc@usc-isib.ARPA Subject: PC Async card on AT Looking at my XT Technical Reference, it looks like J1 disconnects a signal going to bus signal B08. B08 is considered "reserved" except on slot J8, where it is "*CARDSLCTD". This signal is described as intended for indicating that slot J8 was in use, but also mentions that the system board does not use this signal. The J1 signal generated is the NAND of IOR and ENABLE. Looking at my AT Technical Reference, it looks like B08 has been changed to "0WS"!! 0WS is a Zero Wait States signal for fast devices or memory. Dave Mitton. -------