gnu@sun.uucp (John Gilmore) (06/15/85)
> From Ken Shoemaker, 386 Design Team, Intel, Santa Clara, Ca: > If Mot had gone with pipelined address/data on the 68020R16, > I'd guess that their memory access times (addr->data) would go from > 115ns to 170ns. However, they may use pipelining internally to access > their cache, so they can never allow this extra margin for system > designers (does anyone know if this is true?). I think the 68020 drives the address of prefetches (if there's not already a cycle on the bus) but will not assert address strobe if it hits the cache. AS doesn't come out until the addresses are stable anyway, so the cache lookup is overlapped with the address driver propagation delay (and setup time on whoever's receiving the addresses). Serious MMUs start to translate the address before AS anyway, so it actually helps to not have to latch the address, since as fast as the CPU can drive it, the MMU can start looking it up, rather than having it sit on the wrong side of a latch until a strobe comes out. In a 180ns memory cycle it's VERY hard (both for CPU and for memory subsystem) to run with Ken's proposed 170ns addr->data times. It's clear that the 68020 can access memory faster than dynamic ram can respond. There are plenty of solutions developed for mainframes (which have had the same problem for a long time); the on-chip instruction cache is one of them. Ken's overlapping technique may be one that the 68020 design precludes. Got any stats on how many 286 designs use the technique, and how much time is really saved (e.g. is addr->data really the bottleneck)?
phil@amd.UUCP (Phil Ngai) (07/10/85)
>addresses). Serious MMUs start to translate the address before AS >anyway, so it actually helps to not have to latch the address, since >as fast as the CPU can drive it, the MMU can start looking it up, rather But you can't use the address until it is valid, which is the definition of AS anyhow. You also seem to be confusing latch and register. A latch such as the 74373 allows data to flow through it while enabled and holds its output while disabled. A register such as the 74374 stores its input on a clock edge. On the 8086, for example, you would use a 74373 and the address would be available at the time it was valid from the uP plus the prop delay of the latch, which is comparable to the prop delay of the address buffers you would need in a real system anyway. ALE (address latch enable) is not the gating item it would be if a register were used. If a 74374 were used, the address would be available a prop delay after ALE went inactive, which in turn is some setup time after address is valid. -- This is only my opinion and an unofficial one at that. Phil Ngai (408) 749-5720 UUCP: {decwrl,ihnp4,allegra}!amdcad!phil ARPA: amdcad!phil@decwrl.ARPA