[net.micro.68k] prefetching between movl requests

gottlieb@cmcl2.UUCP (Allan Gottlieb) (11/02/83)

Are the two bus requests needed for a 32 bit data item
guarenteed to be consecutive?  In particular, I am
questioning whether an instruction prefetch can come between
the two data requests.

Thanks
Allan Gottlieb
ARPA: GOTTLIEB@NYU
uucp: {floyd,research}!cmcl2!gottlieb

gnu@sun.UUCP (John Gilmore) (11/05/83)

I can't give any Guarantees, but I've never seen a longword fetch or
store be interrupted by other types of accesses (except that the PC pushed
during interrupts is pushed in two pieces with other stack accesses
inbetween).  Note however that if your system arbitrates for the
68000 bus (using BR/BG/BGACK), anybody can break in to a movl with a DMA
cycle.