ken@turtlevax.UUCP (Ken Turkowski) (08/23/84)
A brief look at the 68020 instruction documentation shows that it has
two different types of bit addressing for different instructions.
The bit test, set, clear, etc. instructions address bits within a word
in a little-endian manner, i.e. bit 0 is in the least significant
position, bit 31 in the most significant.
The bit field instructions, on the other hand, address bits (across and
within words) in a big-endian manner, i.e. bit 0 is in the most
significant position, bit 31 in the least.
This proves that it is impossible to make a consistent big-endian
machine! :-)
--
Ken Turkowski @ CADLINC, Palo Alto, CA
UUCP: {amd,decwrl,dual,flairvax,nsc}!turtlevax!ken
ARPA: turtlevax!ken@DECWRL.ARPAian@loral.UUCP (Ian Kaplan) (08/24/84)
In Ken Turkowski's article on the big and little endian addressing used
on the 68020 he commented that Motorola's approach "proved" that a
machine with consistant bit addressing (e.g., all little or big endian)
was impossible. I assume that he was joking. If not perhaps a follow
up article could be submitted clairifing this. It is becoming widely
recognized that consistant (or orthogonal) instruction sets are a
desirable architectural feature. (The NS32016 instruction set is
one example of an orthogonal instruction set.) If consistant
instruction sets are desirable, then it seems obvious that consistant
bit addressing is also desirable.
Ian Kaplan
Loral Data Flow Group
Loral Instrumentation
ucbvax!sdccsu3!loral!ianrcb@rti-sel.UUCP (08/27/84)
If you are looking for a consistant architecture, you should take a look at the VAX architecture. It has the closest to 100% orthogonal instruction set that I have ever seen. As far as bit addressing is concerned, it is entirely little endian. The least significant bit in any size value is ALWAYS bit number 0. And this is with all the bit field instructions of the machine included. The best reference for this is the VAX Architecture Handbook. Randy Buckland Research Triangle Institute ...mcnc!rti-sel!rcb
ken@turtlevax.UUCP (Ken Turkowski) (08/28/84)
=== REFERENCED ARTICLE ===================================
From: ian@loral.UUCP (Ian Kaplan)
Subject: Re: Inconsistent bit addressing in the 68020: big- AND little-endian
In Ken Turkowski's article on the big and little endian
addressing used on the 68020 he commented that Motorola's
approach "proved" that a machine with consistant bit addressing
(e.g., all little or big endian) was impossible. I assume that
he was joking. If not perhaps a follow up article could be
submitted clairifing this. It is becoming widely recognized
that consistant (or orthogonal) instruction sets are a
desirable architectural feature. (The NS32016 instruction set
is one example of an orthogonal instruction set.) If
consistant instruction sets are desirable, then it seems
obvious that consistant bit addressing is also desirable.
=== ARTICLE REFERENCED by ian@loral.UUCP =================
From: ken@turtlevax.UUCP (Ken Turkowski)
Subject: Inconsistent bit addressing in the 68020: big- AND little-endian
...
This proves that it is impossible to make a consistent
big-endian machine! :-)
=================================================================
Note the toungue-in-cheek symbol, ian. Obviously it is possible to
make a consistent big- or little-endian machine. In fact, if you
eliminate the old bit set/clear/test instructions, it becomes a
consistent big-endian machine (See sun!gnu John Gilmore's article
1638@sun.uucp). You just have to get used to the convention that bit 0
is the most significant bit.
--
Ken Turkowski @ CADLINC, Palo Alto, CA
UUCP: {amd,decwrl,dual,flairvax,nsc}!turtlevax!ken
ARPA: turtlevax!ken@DECWRL.ARPAhugh@hcrvax.UUCP (Hugh Redelmeier) (08/31/84)
Randy Buckland says the VAX is entirely little-endian. If you look at the floating point format, it seems to be middle-endian or something: the exponent is in the middle of the fraction, splitting the fraction into two parts. Furthermore, the fraction components contained in succeeding 16-bit words decreases in significance (step-function-endian??). Perhaps the reason is that in changing the precision of integers, the low order bits are important (in narrowing, you pray the high order bits are the same; in widening you make them so), whereas in floating point, the high order fraction bits are the important ones. Thus, for various tricks, you want to address an integer by the location of its low bits, and a float by the location of its exponent & high order bits. At first glance, the VAX f.p. format looks like a botch; at second glance, it makes some sense. Any other thoughts?
dmmartindale@watcgl.UUCP (Dave Martindale) (09/01/84)
As someone else pointed out, the VAX floating point format is big-endian, but that it makes some sense. Look at it this way: The bits adjacent to the decimal point in an integer are at the addressed [byte] location, and higher-order bits in the word/longword/quadword are at successively higher addresses. The bits adjacent to the decimal point in all floating point formats (plus the exponent, of course) are also at the addressed [word] location, with lower-order bits at higher memory addresses. Thus you can use the "feature" of passing the address of a double where the address of its float portion is needed without having to add an offset. The bit field instructions are entirely little-endian, contrary to someone else's comment. Bit fields cross byte, word, and longword boundaries in a consistent manner - the higher-order bits are always at the higher address.
strick@gatech.UUCP (Henry A. Strickland) (09/05/84)
I think it's great that there's such little wrong with 68000 & 68020 that
we're reduced to discussing big & little indians. strick! (-:
--
the clouds project henry strickland
school of ics / ga tech
atlanta ga 30332 { akgua allegra hplabs ihnp4 }!gatech!strick