agn@cmu-cs-k.ARPA (Andreas Nowatzyk) (03/18/85)
According to our information, the min clock frequency for the 68020 is 8Mhz. Does anyone know if it is possible to clock it reliably at a lower rate, say about 1Mhz? How about cooling the chip (to reduce the leakage current)? The reason for this question is that we would like to run it in an simulated environment (Megalogician with PMX) to debug the circuit and the simulator-adapter cannot handle 8 Mhz. I'm also curious for the physical reason for this rather high lower bound. Thanks -- Andreas Usenet: ...!seismo!cmu-cs-k!agn Arpa: Andreas.Nowatzyk@cmu-cs-k.arpa