[net.micro.68k] MAIL WILL NOT SEND - MESSAGE FOR dredge@Fuji.ARPA

davet@oakhill.UUCP (Dave Trissel) (05/17/85)

[...]
Sorry to post this message but I can't get mail to deliver.  In case you're
interested anyway there were two questions on original MC68000 branch and bus
times. First, why does a single word (short) branch instruction require two
bus cycles in the timing charts.  Second, why do long branches take
14 clocks when they fail but only 10 clocks when they are successful.

 To ut-sally!ihnp4!ucbvax!dredge@Fuji.ARPA
 Subject - Branch times


Michael,

What follows only pertains to the MC68000 chip, not necessarily later
versions.

First, the reason why there are two reads even though a Bcc.S is a single word
instruction. An extra word is always fetched due to the nature of the
pipeline and its relationship to the microcode driving it.

Each microcode routine for each instruction always forces a
prefetch request to the bus for the instruction word of the following
instruction.  The instruction pipe is two words, therefore by the time the
Bcc begins execution there has already been yet another word fetched.

A simplified view of the pipe would show that while an instruction is being
executed (word A in the pipe) the next instruction is being decoded (word B
in the pipe while another word is being pre-fetched (read) on the bus.

Thus, even though the Bcc.S is only a single word instruction there is no way
to avoid already having the next word already read in by the time it begins
execution.  This is true for any single word instruction which may cause a
change of control flow (e.g. RTE.)

Your second question is a little more complicated to answer.  It takes one
microcode box (2 clocks) to obtain the condition code register internally.
So, instead of just sitting there for two clocks the microcode precomputes
the destination address AND sets that value into the (internal) scan-PC
register which is used for all instruction fetching by the bus controller.
(Note this in essence changes the pipe to the destination address thus
completing the branch as though the condition is true.)  The next box (2
clocks) allows the determination of the assumed true conditional value by
going though a PLA (Programmed Logic Array.)  If
the branch WAS true then the instruction is essentially complete.  However,
if the branch should not have occured, the scan-PC must be
restored back to its original value before instruction continuation can be
resumed.

Dave Trissel  {ihnp4,seismo}!ut-sally!oakhill!davet