mash@mips.UUCP (John Mashey) (06/06/85)
Doug Pardee writes: > > Some of the notes have indicated that these concerns are one and the > same. Sometimes, but not always. Here's a choice counter-example: > Some RISC machines have a "branch *after* next instruction" operation. > This allows the pipeline to be used more efficiently. It results in > more efficient object code than conventional branch instructions, but > it is a booger-bear to write an effective compiler for. I'm not sure what a booger-bear is, but I guess it indicates difficulty. This turns out not to be true. This function is usually called "filling the branch delay slot", and it's normally done by a pipeline reorganizer that's part of an assembler. It's generally fairly easy to fill [90%+], and it's not exceptionally difficult. See "VLSI Processor Architecture", John Hennessy, IEEE Trans on Computers, Vol C-33, No 12, Dec 1984, or "Reduced Instruction Set Computers", David A. Patterson, Comm ACM V28, 1 (Jan 1985), [for general discusion], or "Postpass code optimization of pipeline constraints", J. L. Hennessy & T. R. Gross, ACM TOPLAS, v5, 3(Jul 83) [for whole paper reorganizer]. -- -john mashey UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mash DDD: 415-960-1200 USPS: MIPS Computer Systems, 1330 Charleston Rd, Mtn View, CA 94043