[net.micro.68k] X86 / 68XXX

freeman@spar.UUCP (Jay Freeman) (06/05/85)

In article <1005@peora.UUCP> jer@peora.UUCP (J. Eric Roskos) writes:

>A major problem with the 286 (and I guess the 386 too, though I haven't
>seen it yet, only the fragmentary descriptions in this newsgroup) is in the
>number of bits available in the instructions themselves for addressing
>data.  This is the primary addressing problen.  The 8086 family has a
>maximum of 16 bits of address for most instructions.

There is no reason that a CPU is limited to one fetch to get the operands
for an instruction.  Many 8- and 16-bit CPUs, including the 8086, have
instructions requiring far more than 8- or 16-bits of operand.  

>                [If you really want an appreciation for the complexity
>of the instruction set, try designing an assembler for it!  Even when you
>think you understand the instruction encoding, you may suddenly discover
>that there are two instructions that don't quite fit...]

Concur.
-- 
Jay Reynolds Freeman (Schlumberger Palo Alto Research)(canonical disclaimer)

jer@peora.UUCP (J. Eric Roskos) (06/07/85)

freeman@spar.UUCP (Jay Freeman at Schlumberger Palo Alto Research, CA),
commenting on my statement that the major problem with 8086 addressing is
not the "maximum segment size", but rather the number of address bits in
the instructions, writes:

>There is no reason that a CPU is limited to one fetch to get the operands
>for an instruction.  Many 8- and 16-bit CPUs, including the 8086, have
>instructions requiring far more than 8- or 16-bits of operand.

I'm somewhat confused as to what this has to do with my original comment.
What I meant was that, in the definition of the instruction set (which
doesn't have anything to do with the number of fetches required to get the
operands in any particular CPU implementation), the address fields are at
most 16 bits long. (This does not include, of course, the small number of
"long" address operands, such as the intersegment call and jump
instructions.)
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