gnu@sun.uucp (John Gilmore) (06/06/85)
> Ken Shoemaker says: I still don't > understand why since Mot gives you seperate address and data busses > that they don't use them better, i.e., present early addresses to > memory systems that could use them to an advantage. This really > does allow faster operation with slower memories at the cost of > more pins on your package. For what it's worth, it seems to me > that Mot is wasting money providing seperate address/data pins > with the utilization that they provide (unless they are not > pad limited on their die, and their yields are such that package > costs are insignificant). I mean, all those extra drivers do take > up die space, and those extra pads could mean that the chip is not > as small or as cheap as it could be.... Well, I was just reading a trade rag that quoted Intel and AMD as having REDUCED the price of the 80186 by 50% to $15-20 for 25K. We got quotes of about $10 for 10MHz 68000's in quantity last month. All those pins are really driving up the price... One advantage of the 680x0 approach is that you don't have to surround your CPU with glue to latch the addresses. You can just wire address pins straight to where they're going and they stay good for the entire cycle. I agree that there might be potential for speed improvement here, so just think -- in a few years when the 68020 seems like a slow machine, they'll have a few more tricks they can pull. Here's some detail on memory cycle and address-to-data times for 68Ks: Part ClkCyc Clk/Mem MemCyc Addr->data 68000L4 250ns 4 1000ns 630ns 68000L10 100ns 4 400ns 230ns 68010L10 100ns 4 400ns 235ns 68000L12 80ns 4 320ns 175ns 68010L12 80ns 4 320ns 175ns 68020R12 80ns 3 240ns 150ns 68020R16 60ns 3 180ns 115ns Note that the 68000L4 was the first to be announced and the 68020R16 is the last to be announced. There's a factor of 5 between the two just in bus cycle times. [I don't think you can buy 68000L4 anymore; just about any die that runs at 4MHz also runs at 8 or more...] > I believe > Mot uses a two level microcode in the 68k and its followons... > (can someone verify this?) Does anyone have any idea what this > means to its performance (with respect jumps and having to fill > up the instruction queue). Do they take two clocks to do a complete > microcode lookup (the first to the first level, the second to the > second level)? The 68000, 68008, and 68010 have the same two-level ucode. There is no jump penalty though. Basically they got tricky and noticed that if they just made the microwords 197 bits wide that it would take up a lot of chip area. Instead, they figured out which bits really HAD to be different for each microinstruction, and which bits might occur in combinations that would occur more than once in the microcode. It turned out that they needed 544 different 17-bit microinstructions to implement the 68000, but by sharing they only needed 336 180-bit nano instructions. There is no "pointer" from the microcode to the nanocode; they are both addressed with the same address (the micro-PC). The trick is that the nanorom is decoded funny and a single row can respond to multiple addresses. These addresses have to be only a few bits different from each other, so they had to be careful about where each microinstruction went in the ROMs. You can read all about it in US Patent #4,325,121 by Tom Gunter and Harry "Nick" Tredennick. I heard that most of the effort in making the 68010 was a large microcode rewrite; the rest of the chip was reputedly similar to a 68000. The patent should be out by now but I haven't tracked it down. I don't know what the microcode for 68020 looks like. Got any similar tricks up your sleeve for the 386, Ken?
kds@intelca.UUCP (Ken Shoemaker) (06/12/85)
> Well, I was just reading a trade rag that quoted Intel and AMD as > having REDUCED the price of the 80186 by 50% to $15-20 for 25K. We got > quotes of about $10 for 10MHz 68000's in quantity last month. > All those pins are really driving up the price... This is comparing apples and oranges, for two reasons: the first is date of introduction of the two products, and the second is that price has little to do with cost. But think about it, how can a 64 pin package ever be cheaper than a 48 pin package? It takes more material, for sure, but in addition to that, it requires more board space and a tester for the device would require additional lines for the extra pins (which usually means a more expensive tester). > > One advantage of the 680x0 approach is that you don't have to surround > your CPU with glue to latch the addresses. You can just wire address > pins straight to where they're going and they stay good for the entire > cycle. I agree that there might be potential for speed improvement > here, so just think -- in a few years when the 68020 seems like a slow > machine, they'll have a few more tricks they can pull. Sure, you are going to drive 2Mbytes of static RAMs (or ROMs?) directly off the pins of the processor? Surely you need an address buffer in there somewhere, or are those not considered "glue"? > > Here's some detail on memory cycle and address-to-data times for 68Ks: > > Part ClkCyc Clk/Mem MemCyc Addr->data > 68000L4 250ns 4 1000ns 630ns > 68000L10 100ns 4 400ns 230ns > 68010L10 100ns 4 400ns 235ns > 68000L12 80ns 4 320ns 175ns > 68010L12 80ns 4 320ns 175ns > 68020R12 80ns 3 240ns 150ns > 68020R16 60ns 3 180ns 115ns > > Note that the 68000L4 was the first to be announced and the 68020R16 > is the last to be announced. There's a factor of 5 between the two > just in bus cycle times. [I don't think you can buy 68000L4 anymore; > just about any die that runs at 4MHz also runs at 8 or more...] Is a factor of 5 good news? Just think, your whole memory system has to be sped up by 5 times! Memory designers may be good, but they aren't THAT good! If Mot had gone with pipelined address/data on the 68020R16, I'd guess that their memory access times (addr->data) would go from 115ns to 170ns. However, they may use pipelining internally to access their cache, so they can never allow this extra margin for system designers (does anyone know if this is true?). -- It looks so easy, but looks sometimes deceive... Ken Shoemaker, 386 Design Team, Intel, Santa Clara, Ca. {pur-ee,hplabs,amd,scgvaxd,dual,qantel}!intelca!kds ---the above views are personal. They may not represent those of Intel.
phil@amdcad.UUCP (Phil Ngai) (06/12/85)
In article <2275@sun.uucp> gnu@sun.uucp (John Gilmore) writes: >Well, I was just reading a trade rag that quoted Intel and AMD as >having REDUCED the price of the 80186 by 50% to $15-20 for 25K. We got >quotes of about $10 for 10MHz 68000's in quantity last month. Actually, we have reduced our price for the 80186 to below $15 in quantity for devices in a plastic leaded chip carrier package. But we haven't been making them very long; you can expect further price reductions as we progress down the volume/price curve. I speculate part of the reason the 68000 is so cheap is because there are so many second sources, and thus, so much competition. Particularly from Japanese vendors. But a 64 pin package will alway be more expensive than a 40 pin package, both for the vendor and for the user. Board space isn't free. >One advantage of the 680x0 approach is that you don't have to surround >your CPU with glue to latch the addresses. You can just wire address >pins straight to where they're going and they stay good for the entire >cycle. Only a very small system can do this. Any reasonable size system will have to buffer the address lines anyway; address latches make great buffers. >Here's some detail on memory cycle and address-to-data times for 68Ks: > > Part ClkCyc Clk/Mem MemCyc Addr->data > 68020R16 60ns 3 180ns 115ns These times are pretty incredible. I seriously doubt anyone will be able to make a 0-wait state memory for the 68020R16 using cost-effective memory devices such as 256K DRAMs. The addition of external memory management hardware (which is required to use a 68K in a multi-tasking environment) will, in addition to consuming more board space, make a 0-wait state memory just about impossible. (for those who don't use DRAMs every day, the average device has an access time of 150 nS. The fastest I have seen run at 100 nS and cost a lot more. I suspect they will never run much faster due to the timing requirements required to set up a row address, operate the row address strobe, provide hold time, set up a column address, operate the column address strobe, and provide hold time for that.) Of course, you can just put wait states in your memory and slow down the system. -- A man could get elected President by promising to put the phone company back together. Phil Ngai (408) 749-5720 UUCP: {ucbvax,decwrl,ihnp4,allegra}!amdcad!phil ARPA: amdcad!phil@decwrl.ARPA
rap@oliveb.UUCP (Robert A. Pease) (06/12/85)
> But think about it, how can a 64 pin > package ever be cheaper than a 48 pin package? It takes more material, > for sure, but in addition to that, it requires more board space and > a tester for the device would require additional lines for the extra > pins (which usually means a more expensive tester). > > Ken Shoemaker, 386 Design Team, Intel, Santa Clara, Ca. > {pur-ee,hplabs,amd,scgvaxd,dual,qantel}!intelca!kds Now hold on a minute. There are other factors in the price of a product. The S100 connectors were expensive as all get out untill they became more popular. Then their price dropped lower than the smaller connectors. -- Robert A. Pease {hplabs|zehntel|fortune|ios|tolerant|allegra|tymix}!oliveb!oliven!rap