ian@wcwvax.UUCP (Ian Kemmish) (08/28/85)
Dave Trissl @ Motorola says the state-saving approach means the processor doesn't have to wait until it knows a write has succeeded without a page fault before starting on the next instruction in the pipeline. In contrast, instruction restart implies waiting until the write works (and therefore that the pipeline isn't as much use as it sounds). Until last week, I would have agreed. BUT . . . I was running some timing tests on my line-drawing algorithm for the Whitechapel MG-1 (uses a NS32016). Basically, it's just a tarted-up Bresenham algorithm with an unwound inner loop of one read-modify-write instruction followed by three register-register instructions. I was trying to special-case nearly-vertical lines by having another loop with two of the register-register instructions removed. After allowing for the time taken to test for the special case, I got a speedup of a massive 10% inside the loop. That sounds like a pretty efficient pipeline to me, folks! (No, I don't know how they do it - I just know what I measured. Anyone else done any similar experiments?)