tve@cernvax.UUCP (tve) (12/12/85)
I would like to build a fast Dynamic RAM for the 68020. Fast means to me 1 wait-state with a 16Mhz '020. Does anyone have any experience with this type of project? Especially did anyone build such a DRAM? I would be *very* glad to hear from you! Some time ago, I asked about 256K - 1M DRAM compatibility. Here's how I think one can be compatible: Socket for 265Kbit and 1Mbit dynamic RAMs: 256Kbit <------------> A8 1|20 Vss Din Din 2|19 CAS Vss WE WE 3|18 Dout Dout RAS RAS 4|17 A6 CAS NC A0 5|16 A3 A9 A0 A2 6|15 A4 A8 A1 A1 7|14 A5 A7 A2 Vcc 8|13 A7 A6 A3 9|12 A5 Vcc 10|11 A4 <---------------------> 1Mbit With this positioning, there are only 3 pins to multiplex, namely pins 8,17 and 19. Any comments welcome, Thorsten von Eicken. ----- Thorsten von Eicken tve@cernvax.UUCP ...!seismo!mcvax!cernvax!tve -----