pyramid@gitpyr.UUCP (Pyramid Technology) (12/20/85)
Has anyone had problems using the Zilog 8530 SCC on the Motorola VME333
Intelligent Communications Controller? We have been trying to debug
a DMA synchronous interface driver and have been getting spurious
interrupts from the 8530 with an interrupt vector number of $ff. We
have traced the problem to the 8530's interrupt acknowledge cycle where
it seems to ocassionally forget to put out its vector on the bus. The
68010 is running at 10 Mhz and the 8530 at 4.9 Mhz. We suspect a timing
problem of some sort but have not been able to isolate it. Anyone have
any similar experience?
Thanks in advance
Jim Stratigos
Tridom Corporation
Marietta, GA 30067
...gatech!akgua!tridom!jas
--
Pyramid Technology
Georgia Insitute of Technology, Atlanta Georgia, 30332
...!{akgua,allegra,amd,hplabs,ihnp4,masscomp,ut-ngp}!gatech!gitpyr!pyramidsfa@ecsvax.UUCP (Sam Averitt) (01/08/86)
This info comes from Howard Crawford at Telex Terminals in Raleigh NC. They have been having similar problems using the 8530 with a 64180. The problem apparently is in the interrupt ack versus vector read timing. The setup time required by the 8530 between int ack and read must be met. Otherwise the vector may come out meaningless. There must also be the right setup time between rec clock and chip clock. The exact values are in the databooks. It is also interesting to note that Apple says not to access the 8530 in the Mac more often than once every 2.2 usec. (from Inside Macintosh) so there must be a fair amount of settling inside the chip. Wayne Sung N C State University
michael@mnetor.UUCP (Michael Barnea) (01/28/86)
> > > This info comes from Howard Crawford at Telex Terminals in Raleigh NC. > They have been having similar problems using the 8530 with a 64180. > The problem apparently is in the interrupt ack versus vector read > timing. The setup time required by the 8530 between int ack and read > must be met. Otherwise the vector may come out meaningless. There must > also be the right setup time between rec clock and chip clock. The > exact values are in the databooks. > It is also interesting to note that Apple says not to access the 8530 > in the Mac more often than once every 2.2 usec. (from Inside Macintosh) > so there must be a fair amount of settling inside the chip. > Wayne Sung > N C State University An article in EDN of April 4 1985 brings an example of interfaces to overcome the inherent 8530 limitations. Although the circuits deal with Intel processor, they are easily adaptable to 68k. The delay in an example circuit can be of course implemented digitally. Michael Barnea, Motorola New Enterprises, Toronto, Canada -- Michael Barnea, UUCP: {allegra, linus, ihnp4, decvax}!utzoo!mnetor!michael BELL: (416)-475-8980 ext. 308