ken@turtlevax.UUCP (Ken Turkowski) (04/07/86)
In article <208@valid.UUCP> gelfand@valid.UUCP (Brooks Gelfand) writes: >The Motorola 68010 has a loop mode operation that works with the >DBcc instruction. In this case the loop is only one instruction deep. There are even further restrictions; you can do a block copy L: movl a0@+,a1@+ dbra d7,L but you can't poll an I/O device's busy bit M: btst #3,a0@ dbeq d7,M and still remain within the cache. Does anybody know why Motorola doesn't allow just any instruction that will fit? -- Ken Turkowski @ CIMLINC, Menlo Park, CA UUCP: {amd,decwrl,hplabs,seismo}!turtlevax!ken ARPA: turtlevax!ken@DECWRL.DEC.COM
tve@cernvax.UUCP (Th.v.Eicken) (04/09/86)
In article <1107@turtlevax.UUCP> ken@turtlevax.UUCP (Ken Turkowski) writes: >>The Motorola 68010 has a loop mode operation that works with the >>DBcc instruction. In this case the loop is only one instruction deep. > >There are even further restrictions; you can do a block copy > L: movl a0@+,a1@+ > dbra d7,L >but you can't poll an I/O device's busy bit > M: btst #3,a0@ > dbeq d7,M >and still remain within the cache. > >Does anybody know why Motorola doesn't allow just any instruction >that will fit? Your I/O device poll can't work for a simple reason: The 68010 has a two word prefech queue and a one word instruction decode register. These three registers hold the loop. Two are used up by the DBRA instruction so only one remains for the looped instruction. BTST as you've used it takes two words, so it can't fit. However I don't know why the following is not permitted: MOVE.W #2,D0 M: BTST D0,(A0) DBEQ D7,M Here the BTST is only one word and thus would fit into the 68010. Anyone knows? Thorsten von Eicken ----- Thorsten von Eicken tve@cernvax.UUCP EP_Division ...!seismo!mcvax!cernvax!tve CERN, Geneva Switzerland -----