jnw@mcnc.UUCP (John White) (09/24/86)
(From Infoworld, Sept 22)
Motorola has announced the 68030, which is almost twice as powerful
as the 68020. Samples are expected in March '87 at around $350, with
production in Oct '87 at $150 to $200. The 68030 is designed for 20MHz,
but the first samples will probably be 16.67MHz.
(From Electronics, Sept 18)
The 68030 is a 128-pin 1.2um CMOS chip. It has a data cache (in addition
to the instruction cache that the 68020 has). It also has an on-chip MMU, and
it uses less than 2 watts.
The MMU is a subset of the 68851. It can address the full 4Gbytes,
and will support 256byte to 32Kbyte pages. The MMU can be disabled, and
an external MMU can be added. Address translation occures at the same time
that the on-chip caches are being checked.
The 68030 is object compatible with the 68020, and looks rather
like a 68020 with a 68851 MMU. The 68030 has the same coprocessor interface
that the 68020 has.
The 256byte instruction cache is organized as 16 entries of 4 long-words
each (the 68020 was 64 entries of 1 long-word each). The data cache is the
same.
There is a new synchronous bus mode where data can be transfered every
2 clocks (the 68020 needed 3 clocks/transfer). There is a pin to allow
the 68030 to switch between the old asynch and new synch modes on the fly.
There is also a burst mode where up to 4 long-words can be transfered at
1 clock/transfer (modulo 4 addressing). This lets a 20MHz 68030 fill
a cache entry at a 64Mbyte/sec transfer rate.
Motorola is not currently trying to get a second source for the
68030, saying this is not needed because they plan to drive prices
down quickly, and because of their JIT service.
Motorola also anounced the 68882, a 20MHz 1.4um CMOS chip that
is pin compatible with the 68881. The 68882 has twice the performance of
the 68881 for old code, and four times the performance if the software
is coded to take advantage of the 68882's pipelined operations.
Volume is expected to begin next summer.
The 68030 sounds like a big improvement over the 68020, although I'll
believe "twice as powerful" when I see some dhrystones. Also, I expect
much of the performance advantage will go away if you don't support the
1 cycle/transfer burst mode, as the caches seem to be arranged so that
the data bus is 128bits wide multiplexed over 32 lines.
John N. White jnw@mcnc
Disclaimer: this is a summary of a preliminary review, so there are at least
two levels of errors.