[net.micro.68k] 68030, summary of preliminary revie

tucker@ccvaxa.UUCP (09/26/86)

>     The 68030 sounds like a big improvement over the 68020, although I'll
>believe "twice as powerful" when I see some dhrystones. Also, I expect
>much of the performance advantage will go away if you don't support the
>1 cycle/transfer burst mode, as the caches seem to be arranged so that
>the data bus is 128bits wide multiplexed over 32 lines.
>
>John N. White   jnw@mcnc

I think this is a bad assumption.  I would imagine that most of the
new perfmorance comes from the fact that it has a DATA CACHE at all.
Also, Motorola has said that much of the new performance comes from
better internal organization of the 68030.  They now use separate
32bit data/address buses internally to each CACHE.  Giving one clock
cycle access instead of two.  Two, the memory unit operates in
parallel to the execution unit.  Three, the virtual address translation
is done while the cache hit is being checked.  If you miss the cache
you already have the physical address if you hit the TLB (i.e. no
PMMU delays on TLB hits).  Four, the internal data buses are clocked
at 80megabytes a second (thats fast!).

As for speed:  A 68020 is usually called a 2mips processor.  I have
read that usually you will get 4mips from a 68030, but if you use
the high speed bus transfer modes you might reach 6 or 8 mips!  That
means that 1 to 1 the 68030 is twice as fast and maybe faster than 
that with some memory tweaking.

tim tucker
Gould Electronics
tucker@gswd-vms.ARPA
..ihnp4!uiucdcs!ccvaxa!tucker