mageau@apollo.uucp (Paul Mageau) (10/09/86)
>>I'm a little disturbed by the reports of the new 68030's on-chip >cache for data accesses. I'm concerned about accesses to I/O devices, >which are (by necessity) memory-mapped in 68xxx machines. > >Problem #1: if the chip decides to cache the value read from an >I/O device status register, subsequent reads will not produce the >current contents of that register. There is a cache inhibit bit in page table that in turn is saved in the on-chip MMU's address translation cache when that page is resident in main memory(i.e the page desciptor is marked valid). If the 68030 detects that the reference being made is unencachable, it will force a cache miss which will in turn force the processor to get the data from the actual control register, bypassing and not allocating in the cache. In general, you shouldn't save dymanic machine state(i.e information that may change without the cache's knowledge) in the data cache. This does not only apply to control/status registers, but also any physical bus transaction(i.e DMA) without flushing the cache. For example, suppose you have a page in memory, marked cachable, that you use to DMA disk block A into. Then suppose the processor accesses this data for whatever reason, which will put it in the cache. Then the program decides to DMA a new disk block into that same physical page. Since the CPU/MMU is not monitoring physical bus traffic it is unaware of this activity. Now, the processes accesses this page, hoping to get the new data, but since the cache wasn't invalidated upon the physical bus entry, it gets the old data. The above problem stems from two problems. First, the 68030 does not monitor phys. bus activity. Secondly, the data and instruction caches are VIRTUAL CACHES, so even if the 68030 did monitor the PHYSICAL bus activity it couldn't invalidate any entries since the cache tag contains only a virtual address. Paul Mageau