henry@utzoo.UUCP (Henry Spencer) (01/08/85)
The following is some interesting information, from a source I will not
name (and don't bother asking for more info, you're getting all I've got),
about a forthcoming chip set from DEC, the "Microvax 2 [II?]" chips.
The cpu chip, which implements the Microvax instruction set (i.e. VAX
minus a few of the sillier things) and has memory management on-chip,
is the 78032. (This is pronounced "seven-eighty-thirty-two" for some
reason, not "seventy-eight-oh-thirty-two".) The floating-point chip,
a tightly-coupled coprocessor, is the 78132. There is a DMA controller
(78532), a DRAM controller (78584), and a vectored-interrupt chip (78516)
to match. In-Circuit-Emulation goodies will follow.
The chips are bug-free (or roughly so) in the lab, to the extent that
both VMS and Ultrix are already running on them. Benchmarking is
being done, so it can be safely assumed that they are running at near-final
clock speeds as well.
"What about the benchmarking", you ask... The story I have is that they
are consistently faster than the 750, although not consistently up to a
780. Some instructions are actually a bit faster than on a 780, but the
overall speed is somewhat lower.
They will probably appear first in a system-level product, which will be
a Q-bus machine with a private (i.e. fast) cpu-to-memory bus. They will
then work their way down to board-level and chip-level products.
"When", you ask... My source claims that announcement timing is the
subject of hot debate, but the word is "months".
--
Henry Spencer @ U of Toronto Zoology
{allegra,ihnp4,linus,decvax}!utzoo!henryed@mtxinu.UUCP (Ed Gould) (01/16/85)
> The cpu chip, which implements the Microvax instruction set (i.e. VAX > minus a few of the sillier things) I understand that although the uVAX I has a restricted instruction set, the II has the whole thing. It's the fallout of a 5-chip implementation of a 780 at 780 speed! (The overall speed was targeted at the wame as a 780 - a few instructions differ.) > "When", you ask... My source claims that announcement timing is the > subject of hot debate, but the word is "months". > -- I've heard that the announcement has been delayed from "soon" (early '85) to June or July or so, with delivery around the end of the year. > Henry Spencer @ U of Toronto Zoology > {allegra,ihnp4,linus,decvax}!utzoo!henry -- Ed Gould mt Xinu, 739 Allston Way, Berkeley, CA 94710 USA {ucbvax,decvax}!mtxinu!ed +1 415 644 0146
henry@utzoo.UUCP (Henry Spencer) (01/20/85)
> > The cpu chip, which implements the Microvax instruction set (i.e. VAX > > minus a few of the sillier things) > > I understand that although the uVAX I has a restricted instruction > set, the II has the whole thing. ... My informant, who's in a position where he ought to know, definitely identified the instruction set as "Microvax", not "VAX". Unless I misunderstood him... > I've heard that the announcement has been delayed from "soon" (early > '85) to June or July or so, with delivery around the end of the year. This is plausible. It sounds like the chips are pretty much ready to go; my source says some customers have samples for testing. -- Henry Spencer @ U of Toronto Zoology {allegra,ihnp4,linus,decvax}!utzoo!henry
peterb@pbear.UUCP (01/22/85)
From what I have heard, The chip set is reduced to one chip that incorporates the CPU, the FPU and th MMU onto a 68 pin monster that drops about 5 watts of juice. The clock is up to a speed of 31 MHz, and the instructions are not all implemented directly, some of the rare/large instructions are implemented via EMT traps. The speed places it between a 750 and a 780 (closer to the 780 I believe). This is the latest die from Digital, and I expect more since there exist some timing problems, and some undocumented bugs/features that are be quite annoying. Peter Barada ima!pbear!peterb