mdolin@nugipsy.UUCP (Mike Dolin) (08/26/86)
Can anyone help me with a simple generic description of VME?
(Versabus Modulo Europa)
It's a 32-bit architecture system used for I/O processing.
If I'm on the wrong net.group, which one would be more appropriate?
Thanks in advance.
Reguards,
Mike Dolin
Gould Computer Systems Division
Ft. Lauderdale, Florida
.....!{brl-bmd,pur-ee,sun}!gould!mdolin
Standard disclaimer applies.jon@msunix.UUCP (Jonathan Hue) (09/03/86)
In article <35@houligan.UUCP>, mdolin@nugipsy.UUCP (Mike Dolin) writes: > Can anyone help me with a simple generic description of VME? We've got these fairly nice specs of the VME bus in really thick three-ring binders that say United Technologies/Signetics on the cover. I believe that you can buy these VME bus specs from any of the companies that participated in the VME bus design. Try contacting your local Signetics office. Quite simply put, it's an asynchronous bus, with up to three 96-pin connectors called P1, P2, and P3. P1 has 24 bits of address, and 16 bits of data, P2 is used for user defined I/O, and P3 is for the expansion to 32 bits for address and data. P3 is optional, and so is P2, but most backplanes have the connectors for the P2 bus since the smallest boards are double height. P1 is required, of course. The connectors are stacked vertically, each one is 3 pins wide and 32 high, and are the pin and socket variety. I believe both ends are terminated into 330 and 470 ohms, with the 330 to ground. It supports multiple masters of course. The signals sort of look like a 68k pinouts, you get 23 address lines, 16 data lines, four levels of bus request/bus grant in/bus grant out for 12 more pins, five address modifier lines which are sort of like the function codes of the 68k, you pick address spaces like system short I/O, user long program, and stuff like that, two data strobes (DS0 and DS1), WRITE, DTACK, address strobe, seven levels of interrupt request along with IACK, IACKIN, and IACKOUT, bus error, bus busy, bus clear, long word (for 32 bit transfers), three lines for exceptional conditions (ACFAIL, SYSFAIL, and SYSRESET), and a bunch of power and ground pins. There are also two signals, SERCLK and SERDAT which are supposed to be for multiprocessor communication, but I don't know much about them (or any of this stuff, for that matter). The P3 bus adds 8 more address lines and 16 more data lines. I can't recall what else it adds. There are a bunch of unused lines I think, so if you run out of user defined stuff on P2 you have some more to play with. There is also the VMX bus, which is for local memory so you can reduce traffic on the VME bus and speed things up, and a VMS bus, which is for serial communication between processors (somehow related to the SERDAT and SERCLK pins on P1 I guess). Specs for these are included with VME specs. Don't be suprised to see boards from vendors violating VME bus (timing) specs. We've got more than a couple boards which don't hold addresses stable throughout the period that they are supposed to drive them, which forced us to add latches where none should have been needed. I don't know if there is a group where you can discuss digital electronic topics. Maybe net.arch, or maybe we need a net.digital. I mean, there's a net.analog; how many net readers are analog circuit designers? "If we did it like everyone else, Jonathan Hue what would distinguish us from Via Visuals Inc. every other company in Silicon Valley?" sun!sunncal\ >!leadsv!msunix!jon "A profit?" amdcad!cae780/
henry@utzoo.UUCP (Henry Spencer) (09/11/86)
> I don't know if there is a group where you can discuss digital electronic > topics. Maybe net.arch, or maybe we need a net.digital. Not net.arch, please; that's for computer architecture, not digital circuit design. Net.micro has actually been used for such things in the past. There wasn't sufficient volume to justify a separate group. > I mean, there's a net.analog; how many net readers are analog circuit > designers? The latest revised list of the Great Newsgroup Renaming has net.analog in fact being renamed to something like "sci.circuits" (I forget the exact choice of name, it's along those lines) since there's an obvious need for a place to put other types of circuit design and it's not a big enough topic for multiple newsgroups. -- Henry Spencer @ U of Toronto Zoology {allegra,ihnp4,decvax,pyramid}!utzoo!henry