arpa-bboard@ucbvax.ARPA (05/25/85)
From: Mario.Barbacci@cmu-sei.arpa
PROGRAM
7TH INTERNATIONAL SYMPOSIUM ON
COMPUTER HARDWARE DESCRIPTION LANGUAGES AND THEIR APPLICATIONS
CHDL-85
AUGUST 29-31, 1985
KEIDANREN BUILDING
TOKYO, JAPAN
Sponsored by the International Federation for Information Processing (IFIP)
and the Information Processing Society of Japan (IPSJ), organized by IFIP TC-10
and IFIP WG 10.2, in cooperation with IEEE-CS, ACM, GI, and NTG.
General Chairman: Program Chairman:
Professor Tohru Moto-oka Dr. Cees Jan Koomen
Department of Electrical Engineering Philips International
University of Tokyo Product Development Coordination
Hongo, 7 chome VO-1, P.O. Box 218
Bunkyo-ku 5600 MD Eindhoven,
Tokyo, Japan The Netherlands
telephone (212) 2111 ext. 6652 telephone (31) (40) 784962
ArpaNet: Philips@sri-csl
For information about local arrangements contact:
Dr.Takao Uehara (Chairman)
Computer-Based Systems Laboratory Conference Secretariat, CHDL 85
Fujitsu Laboratories Ltd. Business Center for Academic Societies
1015 Kamikodanaka Nakahara-ku 4-16 Yayoi 2-chome, Bunkyo-ku
Kawasaki 211, Japan Tokyo 113, Japan
telephone (81) (44) 777 1111 X6280 telephone: (81) (3) 815-1903
telex 3842 122
THURSDAY, AUGUST 29TH
09:00-10:00 Keynote Speech -- J. Darringer (IBM)
10:00-10:30 Break
10:30-12:00 SPECIFICATION 1 (chairperson: J. Jess)
On the Axiomatic Specification of Computer Architectures.
S. Dasgupta, J. Heinanen (University of Southwestern Louisiana,
USA)
An Algebraic Approach to the Specification and Realization of
VLSI Designs. G.C. Gopalakrishnan, D.R. Smith. M.K. Srivas
(SUNY, USA)
Describing and Reasoning about Circuit Behaviour by Means of
Time Functions. P. Amblard, P. Caspi, N. Halbwachs (IMAG,
France)
12:00-14:00 Lunch and Invited Paper
Testable Design and Design Language. K. Kinoshita (Hiroshima
University, Japan)
14:00-15:30 SYNTHESIS 1 (chairperson: M. Barbacci)
Design Method Based Logic Synthesis. S. Takagi (NTT, Tokyo,
Japan)
An RTL Behavioural Description based Logic Design CAD System
with Synthesis Capability. Y. Nakamura, Y. Sakata, K. Oguri
(NTT, Yokosuka, Japan)
Synthesis of Modular Controllers from Cap/DSDL Descriptions.
R. Bruck, B. Kleinjohann, F.J. Rammig (University of Dortmund,
University of Paderborn, FRG)
15:30-16:00 Break
16:00-17:30 VERIFICATION 1 (chairperson: E. Horbst)
Automatic Verification of Sequential Circuits using Temporal
Logic. M. Browne, E.M. Clarke, D. Dill, B. Mishra
(Carnegie-Mellon University, USA)
VERENA: A Program for Automatic Verifications of the Refinement
of Register Transfer Description into a Logic Description.
W. Grass, N. Schielow (University of Hamburg, FRG)
Logic Design Assistance with Temporal Logic. M. Fujita,
H. Tanaka, T. Moto-Oka (University of Tokyo, Japan)
18:00 RECEPTION
FRIDAY, AUGUST 30TH
09:00-10:30 SPECIFICATION 2 (chairperson: S. Dasgupta)
PROLOG for Specification, Verification and Simulation.
S. Gregory, R. Neely, G. Ringwood (Imperial College, UK)
ASYL/EFSM: A Formal Specification Language and its Environment.
M. Daniels, H.A. Hansson (Uppsala University, Sweden)
The Application of CHDL's to the Abstract Specification of
Hardware. H. Eveking (Technical University Darmstadt, FRG)
10:30-11:00 Break
11:00-12:00 SIMULATION 1 (chairperson: F.J. Rammig)
Fast Interpretation of Instruction Sets: Implementation and
Applications. J.W. Davidson (University of Virginia, USA)
Performance Evaluation of a Pipelined VLSI Architecture using
the Graph Model of Behaviour. J.T. Hsieh, A.R. Pleszkun, M.K.
Vernon (University of Wisconsin, USA)
12:00-14:00 Lunch and Invited Paper
Configuration Management and Consistency Control in Integrated
CAD Systems. L.D.J. Eggermont, G. Marechal (Philips,
Netherlands)
14:00-15:30 TOOL INTEGRATION 1 (chairperson: T. Sudo)
Several Steps towards a Circuits Integrated CAD System: ARCADE.
J. Mermet (IMAG, France)
Overview of the CASCADE Multi-level Hardware Description
Language and its Mixed-Mode Simulation Mechanisms. D. Borrione,
C. le Faou (IMAG, France)
RTL Test Generation and Validation for VLSI: An Integrated Set
of Tools for KARL. S. Morpurgo, A. Hunger, M. Melgara, C. Segre
(Olivetti, Italy; University of Aachen, FRG; CSELT, Italy)
15:30-16:00 Break
16:00-17:30 CHDL (chairperson: R. Hartenstein)
ADA as a Hardware Description Language: An Initial Report. M.R.
Barbacci, S. Grout, G. Lindstrom, M. Maloney, E. Organick,
D. Rudisill (Carnegie-Mellon University, University of Utah,
Martin-Marietta Corp., USA)
The Design Rationale of ELLA, a Hardware Design and Description
Language. J.D. Morison, N.E. Peeling, T.L. Thorp (Royal
Signals and Radar Establishment, UK)
HSL-FX: A Unified Language for VLSI Design. T. Hoshino,
O. Karatsu, T. Nakashima (NTT, Japan)
18:00 BANQUET
SATURDAY, AUGUST 31ST
09:00-10:30 TOOL INTEGRATION 2 (chairperson: D. Borrione)
A Unified Representation for Design Information. D.W. Knapp,
A.C. Parker (University of Southern California, USA)
A Database Approach to Design Data Management and Programming
Support for ELLA, a High-level CHDL. N.E. Peeling, J.D. Morison
(Royal Signals and Radar Establishment, UK)
CADOC System: a Tool for Multilevel Description and Test
Program Generation for VLSI Circuits. C. Bellon, M. Crastes de
Paulet, S. Hanriat, J. Rarivomanana, G. Saucier (IMAG, France)
10:30-11:00 Break
11:00-12:00 SYNTHESIS 2 (chairperson: A. Yamada)
OCCAM to CMOS: Experimental Logic Design Support System.
T. Mano, F. Maruyama, K. Hayashi, T. Kakuda, N. Kawato,
T. Uehara (Fujitsu, Japan)
Synthesizing Circuits from Behavioural Level Specifications.
W. Rosenstiel, R. Camposano (University of Karlsruhe, FRG)
12:00-13:30 Lunch
13:30-15:30 VERIFICATION 2 (chairperson: C.J. Koomen)
Simulation and Verification: Related Techniques for Hardware
Analysis. G.J. Milne (University of Edinburgh, UK)
Specification and Verification using Higher-Order Logic . F.K.
Hanna, N. Daeche (University of Kent, UK)
The Application of Formal Specification and Verification to a
Hardware Design. J. Herbert (Cambridge University, UK)
Experience in CONLAN based formal Verification of HDL's.
G. Cabodi, P. Camurati, G. Crosetti, P. Prinetto (Politecnico
of Torino, Italy)
15.50-16:00 Break
16:00-17:00 SIMULATION 2 (chairperson: M.K. Vernon)
A Multilevel Hierarchical Simulator based on LALSD II. S.Y.H.
Su, B. Amini (SUNY, USA)
Automated Logic Verification System using MIXS Verifier and
Hardware Logic Simulator HAL. T. Sasaki, N. Nomizu, H. Tanaka,
S. Kato, M. Kuwata, A. Yamada (NEC, Japan)
17:00 CLOSURE